Cadence Design Systems has entered into a definitive agreement to acquire Jasper Design Automation for approximately $170 million in cash. Jasper had approximately $24 million of cash, cash equivalents and short-term investments as of December 31, 2013.
Jasper Design Automation is a market and technology leader in the fast-growing formal analysis sector, providing multiple verification solutions (Verification Apps) built on the JasperGold platform. Jasper's customers include many of the top systems, semiconductor and IP companies. These companies, which are also Cadence customers, are increasingly adopting formal analysis to complement traditional verification methods, so as to better address the challenge of verifying increasingly complex and flexible IP designs and systems-on-chip (SoCs). With verification representing over 70% of the cost of developing a system-on-chip, it has become the top system and SoC development challenge and is the critical factor for time-to-market.
"Jasper's products are recognized as the technology leaders in formal analysis, targeting complex verification challenges and increasing overall verification productivity," said Charlie Huang, senior vice president of the System & Verification Group and Worldwide Field Operations at Cadence. "Jasper's formal analysis solutions are used by customers today alongside Cadence's metric-driven verification flow to form a broad verification solution. We look forward to welcoming Jasper's strong formal development expertise and skilled team to Cadence."
Jasper's technology strengths are highly complementary to Cadence's System Development Suite, which has been the standard bearer for integrated system verification solutions since 2011. The combination will expand differentiation of the industry's strongest and broadest system verification platform, and will be tightly integrated with Cadence's common debug analysis, formal and semi-formal solutions, simulation, acceleration, emulation and prototyping platforms, while leveraging its unified verification planning and metric-driven verification flow. In addition, the combination of extensive dynamic and formal VIP portfolios will be particularly well suited to enable embedded processor system verification.
