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SK hynix, Sandisk unveil first open standard for High Bandwidth Flash to ease AI memory bottlenecks
2026-08-04
SK hynix and Sandisk have unveiled the industry's first open standard for High Bandwidth Flash (HBF), a new storage technology designed to bridge the gap between high-bandwidth memory (HBM) and solid-state drives (SSDs) as AI workloads place growing demands on enterprise infrastructure.
The specification, announced at the Future of Memory and Storage (FMS) 2026 conference in California, is intended to establish HBF as an industry standard rather than a proprietary technology. The companies published the specification through the Open Compute Project (OCP) to encourage adoption across the AI ecosystem.
HBF introduces a new memory tier that combines the high-speed data transfer characteristics of HBM with the larger storage capacity of NAND flash. SK hynix said the technology is designed to address the growing bandwidth and capacity constraints created by large-scale AI inference workloads, where rapidly expanding datasets increasingly exceed the capabilities of existing memory hierarchies.
The standard defines capacities of up to 512GB using 8-high and 16-high NAND die stacks and supports bandwidth ranging from approximately 0.4 TB/s to 3.0 TB/s, allowing vendors to scale performance for different AI infrastructure requirements.
A key element of the specification is its adoption of Universal Chiplet Interconnect Express (UCIe), an open industry standard for connecting semiconductor chiplets. By using UCIe, HBF is designed to integrate with multiple processor architectures, including CPUs and GPUs, rather than being tied to a specific hardware platform.
The specification also defines electrical interfaces, packaging requirements, software input/output guidelines and reliability characteristics, providing a common framework for hardware vendors developing HBF-based products.
The announcement comes about six months after SK hynix and Sandisk established an HBF consortium to develop the technology. The consortium has since expanded to include companies such as Google and AI chip startup Tenstorrent, with SK hynix saying it expects broader industry participation as the ecosystem develops.
At FMS 2026, SK hynix executives said the rapid growth of agentic AI is driving demand for what the company describes as a tiered memory architecture, in which multiple memory technologies operate together to optimise performance, capacity and cost across AI systems.
Rather than relying on a single memory technology, SK hynix argues that future AI infrastructure will require coordinated use of HBM, HBF, DRAM and SSDs to efficiently support increasingly data-intensive inference workloads.
The introduction of an open HBF specification reflects the semiconductor industry's broader effort to standardise next-generation memory technologies as hyperscalers and enterprise organisations invest heavily in AI infrastructure. If widely adopted, HBF could become an additional layer in future AI servers, helping address one of the industry's biggest technical challenges—delivering both high bandwidth and large memory capacity without relying exclusively on increasingly expensive HBM.
The specification, announced at the Future of Memory and Storage (FMS) 2026 conference in California, is intended to establish HBF as an industry standard rather than a proprietary technology. The companies published the specification through the Open Compute Project (OCP) to encourage adoption across the AI ecosystem.
HBF introduces a new memory tier that combines the high-speed data transfer characteristics of HBM with the larger storage capacity of NAND flash. SK hynix said the technology is designed to address the growing bandwidth and capacity constraints created by large-scale AI inference workloads, where rapidly expanding datasets increasingly exceed the capabilities of existing memory hierarchies.
The standard defines capacities of up to 512GB using 8-high and 16-high NAND die stacks and supports bandwidth ranging from approximately 0.4 TB/s to 3.0 TB/s, allowing vendors to scale performance for different AI infrastructure requirements.
A key element of the specification is its adoption of Universal Chiplet Interconnect Express (UCIe), an open industry standard for connecting semiconductor chiplets. By using UCIe, HBF is designed to integrate with multiple processor architectures, including CPUs and GPUs, rather than being tied to a specific hardware platform.
The specification also defines electrical interfaces, packaging requirements, software input/output guidelines and reliability characteristics, providing a common framework for hardware vendors developing HBF-based products.
The announcement comes about six months after SK hynix and Sandisk established an HBF consortium to develop the technology. The consortium has since expanded to include companies such as Google and AI chip startup Tenstorrent, with SK hynix saying it expects broader industry participation as the ecosystem develops.
At FMS 2026, SK hynix executives said the rapid growth of agentic AI is driving demand for what the company describes as a tiered memory architecture, in which multiple memory technologies operate together to optimise performance, capacity and cost across AI systems.
Rather than relying on a single memory technology, SK hynix argues that future AI infrastructure will require coordinated use of HBM, HBF, DRAM and SSDs to efficiently support increasingly data-intensive inference workloads.
The introduction of an open HBF specification reflects the semiconductor industry's broader effort to standardise next-generation memory technologies as hyperscalers and enterprise organisations invest heavily in AI infrastructure. If widely adopted, HBF could become an additional layer in future AI servers, helping address one of the industry's biggest technical challenges—delivering both high bandwidth and large memory capacity without relying exclusively on increasingly expensive HBM.
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